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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-05602-5E
Microprocessor SPARClite
CMOS
Peripheral LSI for SPARClite
MB86941/942
s DESCRIPTION
MB86941 and MB86942 are dedicated peripheral LSIs for SPARClite*. The MB86941 and MB86942 are designed to enable compact configuration of high-performance systems with SPARClite architecture, and provide the following features. * : SPARC is a registered trademark of SPARC International base on technology developed by Sun Microsystems, Inc. SPARClite is a trademark of SPARC International, Inc. licensed exclusively to Fujitsu Microelectronics, Inc.
s FEATURES
Direct connection to SPARClite Register read/write in 2 clock cycles up to 30MHz. Register read/write in 3 clock cycles at 40MHz (MB86941) or 50MHz (MB86942). Built-In On-Chip Modules: * Interrupt controller Interrupt input: 15 channels Each interrupt input has independent masking and trigger mode settings * 16-bit timer: 4 channels Two of the four channels have prescalers Each channel has five independent mode operations MODE0 : Periodical-interrupt MODE1 : Timeout-interrupt MODE2 : Square wave generator
(Continued)
s PACKAGE
144-pin Plastic QFP
(FPT-144P-M03)
MB86941/942
(Continued) MODE3: Programmable one shot (software trigger) MODE4: Programmable one shot (external trigger)
* SDTR (Serial data transmitter receiver): 2 channels MB89251A type * Timing control, CS expansion Generates read, write and data strobe signals according to the requirements of external devices. * SIO (Synchronous serial input/output) Simple synchronous type serial input/output * I/O port, 16-bit Individual direction control by bit 5V single power supply (MB86941), 3.3V single power supply (MB86942) Upward pin compatibility with MB86940C
2
MB86941/942
s PIN ASSIGNMENT
(TOP VIEW)
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
N.C. IPD15 IPD14 IPD13 IPD12 IPD11 VSS D7 D6 IPD10 IPD9 N.C. IPD8 IPD7 IPD6 D5 D4 VSS VDD D3 D2 IPD5 IPD4 IPD3 IPD2 D1 D0 VSS OUT3 OUT2 IPD1 IN2 CLK2 IN3 CLK3 VDD SIRXD SITXD SIIRQ N.C. WSEL SICLK N.C. N.C. VSS RESET# CLOCK AS# RD/WR# CS# N.C. D8 D9 VDD VSS D10 D11 RS4 RS3 RS2 RS5 RS1 RS0 D12 D13 VSS D14 D15 IRQ15 IRQ14 IRQ13 IRQ12 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
INDEX
IPD0 CLK1 IN1 ACK1 PRSCK1 OUT1 VSS OUT0 PRSCK0 ACK0 IN0 CLK0 DSR1# CTS1# RTS1# TRNDT1 DTR1# VSS VDD SYBRK1 TRDY1 RCLK1 RCVDT1 RDYOUT# TCLK1# DS# TEMP1 VSS RRDY1 RRDY0 TEMP0 TCLK0# RCVDT0 A1 A0 RCS#
* : Only for MB86941. Open for MB86942.
VDD IRQ11 IRQ10 IRQ9 IRQ8 IRQ7 IRL3 IRL2 VSS IRL1 IRL0 IRQ6 IRQ5 IRQ4 IRQ3 CS0# READY2#* VDD VSS READY1# CS1# IRQ2 IRQ1 CS2# CS3# DSR0# CTS0# RTS0# TRNDT0 VSS DTR0# SYBRK0 TRDY0 RCLK0 RE# WE# (FPT-144P-M03)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
3
MB86941/942
s BLOCK DIAGRAM
IRL < 3 : 0 > /2 1 / 2 Clock 1 / 1 Clock CLOCK RESET# AS# RD/WR# CS# RS < 5 : 0 > D < 15 : 0 > READY1# READY2#* WSEL Timer RCS# A<1:0> RDYOUT# CS0# to CS3# RE# WE# DS# Timer IP I/O Port IPD < 15 : 0 > TM2 Timer SICLK SIRXD SITXD SIIRQ DSR0#, CTS0# RTS0#, DTR0# TEMP0, TRDY0 TRNDT0 TCLK0# RCLK0, RCVDT0 SYBRK0 RRDY0 DSR1#, CTS1# RTS1#, DTR1# TEMP1, TRDY1 TRNDT1 TCLK1# RCLK1, RCVDT1 SYBRK1 RRDY1 * : Only for MB86941. Open for MB86942. Internal Data Bus Internal Control Bus SDTR1 Serial Data Transmitter Receiver SIO Serial Data Input Output Timer SDTR0 Serial Data Transmitter Receiver CLK2 IN2 OUT2 TM3 CLK3 IN3 OUT3 TM1 CLK1 IN1 OUT1 RCSTG Read/Write Chip Select Timing Generator TM0 CLK0 IN0 OUT0 PRS1 Prescaler ACK1 PRSCK1 PRS0 Prescaler ACK0 PRSCK0 BIU Bus Interface Unit Reset IRC Interrupt Request Controller IRQ1 to IRQ15
4
MB86941/942
s DESCRIPTION OF BLOCK FUNCTIONS
1. BIU (Bus Interface Unit)
This block receives MPU (SPARClite) bus signals and bus controls signals (CLOCK, AS#, RD/WR#, CS#, ADR6 to ADR2, D<15:0>) and generates control signals for accessing MB86941/MB86942 internal resources. It also returns that Ready signal to the MPU which corresponds to the access time of each of such resources.
2. IRC (Interrupt Request Controller)
This block provides 15-channel interrupt input signals to transmit the interrupt level IRL <3:0> for each interrupt to the SPARClite.
3. TM (Timer) and PRS (Prescaler)
TM0 to TM3 are 16-bit timers serving as periodic interrupt generation timers, a watchdog timer, and an external event counter. The operating clock can be selected from among the internal clock, the clock frequency-divided by the prescaler, and the external clock. Prescalers 0 and 1 are linked with timer channels 0 and 1, respectively. Each of the prescalers is initialized upon loading (or reloading) of the timer initial value of the corresponding timer.
4. SDTR (Serial Data Transmitter Receiver)
SDTR0 and SDTR1 are serial data transmitter/receiver modules programmable for control of transmission and reception. The programming model is the same as that for the MB89251A.
5. RCSTG (Read/Write Timing Generator)
This module generates read, write, and data strobe signals conforming to the required timings for external connection of other devices. The assert timing and pulse width of each signal to be generated is programmable.
6. IP (I/O Port)
There are 16 I/O ports. The input/output direction of each port can be set by the control register.
7. SIO (Serial Data Input Output)
This block is a clock-synchronous serial interface. The transfer clock signal can be set to the internally generated or externally input one. The SIO outputs data to be transmitted and inputs received data in synchronization with the transfer clock signal.
5
MB86941/942
s PIN DESCRIPTION
IRL < 3 : 0 >
IRQ15 to IRQ1
MB86941/2
CLOCK RESET# AS# MPU INTERFACE (34/33) RD/WR# CS# RS < 5 : 0 > D < 15 : 0 > READY1# READY2#* WSEL RCS# A<1:0> RDYOUT# RCSTG (11) CS0# to CS3# RE# WE# DS# IP (16) IPD < 15 : 0 > SICLK SI0 (4) SIRXD SITXD SIIRQ DSR1# RTS1# DTR1# CTS1# TRNDT1 TEMP1 TRDY1 TCLK1# RCVDT1 RCLK1 SYBRK1 RRDY1 DSR0# RTS0# DTR0# CTS0# TRNDT0 TEMP0 TRDY0 TCLK0# RCVDT0 RCLK0 SYBRK0 RRDY0 CLK2 IN2 OUT2 CLK3 IN3 OUT3 ACK1 PRSCK1 CLK1 IN1 OUT1 ACK0 PRSCK0 CLK0 IN0 OUT0
IRC (15)
TIMER & PRESCALER (16)
SDTR1 (12)
SDTR0 (12)
VDD: (6) VSS: (12) N.C.: (6/7) Note: Numerical value of a parenthesis shows numbers of PIN. * : Only for MB86941. Open for MB86942.
6
MB86941/942
1. MPU INTERFACE SIGNALS (34/33)
Pin symbol RESET# I/O I Pin no. 118 Reset Pin name Description Reset input pin Input an "L" signal to this pin to reset the chip. System clock input pin The chip contains some modules that use the clock signal from this pin (not divided), and other modules that use the clock signal divided in half. Clock not divided: BIU, RCSTG, IP Clock divided: IRC, PRS0, PRS1, TM0 to TM3, SDTR0, SDTR1, SIO Address strobe input pin Input an "L" signal to this pin to determine register access according to the signals input to the RS<5:0>, CS#, and RD/WR# pins. Read/write input pin Input an "H" signal to designate a read cycle, or an "L" signal to designate a write cycle. Chip select input pin Register select input pin The combination of input signals to the RS<5:0> and CS# pins determines which register is accessed. The RS5 pin has internal pull-down resistance (MB86941 only). Data ready output pin MB86941: Open drain output with 12mA "L" drive capability. Drives an "H" level signal for 3ns before going to High-Z state. MB86942: Normal output. READY2# signal deleted. If the READY generator circuit in the MPU is used, it is not necessary to connect this pin to the MPU. Wait select input pin Input to this pin determines the interface timing with the MPU. Fix "L" to set register read/write access to 3 cycles, or fix "H" to set register read/write access to 2 cycles. This pin has internal pull-up resistance (MB86941 only).
CLOCK
I
119
Clock
AS#
I
120
Address Strobe
RD/WR# CS# RS0 RS1 RS2 RS3 RS4 RS5 READY1#
I I I I I I I I O
121 122 135 134 132 131 130 133 20
Read/Write Chip Select Register Select 0 Register Select 1 Register Select 2 Register Select 3 Register Select 4 Register Select 5 Ready 1
READY2#
O
17
Ready 2
WSEL
I
113
Wait Select
(Continued)
7
MB86941/942
(Continued)
Pin symbol D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 IRL0 IRL1 IRL2 IRL3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O Pin no. 82 83 88 89 92 93 100 101 124 125 128 129 136 137 139 140 11 10 8 7 Pin name Data Bus 0 Data Bus 1 Data Bus 2 Data Bus 3 Data Bus 4 Data Bus 5 Data Bus 6 Data Bus 7 Data Bus 8 Data Bus 9 Data Bus 10 Data Bus 11 Data Bus 12 Data Bus 13 Data Bus 14 Data Bus 15 Interrupt Request Level 0 Interrupt Request Level 1 Interrupt Request Level 2 Interrupt Request Level 3 Interrupt request output pin These pins are used to generate interrupts to the MPU and notify the interrupt level. Data I/O port These pins are used to transfer register read/write data. Description
8
MB86941/942
2. INTERRUPT REQUESTS (15)
Pin symbol IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 I/O I I I I I I I I I I I I I I I Pin no. 23 22 15 14 13 12 6 5 4 3 2 144 143 142 141 Pin name Interrupt Request 1 Interrupt Request 2 Interrupt Request 3 Interrupt Request 4 Interrupt Request 5 Interrupt Request 6 Interrupt Request 7 Interrupt Request 8 Interrupt Request 9 Interrupt Request 10 Interrupt Request 11 Interrupt Request 12 Interrupt Request 13 Interrupt Request 14 Interrupt Request 15 Interrupt request pin Interrupt receiving priority: IRQ15 is highest priority and IRQ1 is lowest. A choice of four interrupt waveforms is available by mode setting for each of the 15 pins independently, including "H" level, "L" level, rising edge, and falling edge. Each input has a filtering function for short pulse signals, by which an interrupt request is recognized once a signal is detected at active level at three successive rising edges of the internal clock signal. Once an interrupt request is detected, it passes through priority control and masking control and is output at the IRL<3:0> pins as an interrupt request to the MPU. If these pins are not used, they should be fixed at inactive level. Description
9
MB86941/942
3. TIMER SIGNALS (16)
Pin symbol CLK0 IN0 OUT0 CLK1 IN1 OUT1 CLK2 IN2 OUT2 CLK3 IN3 OUT3 ACK0 I/O I I O I I O I I O I I O I Pin no. 61 62 65 71 70 67 76 77 79 74 75 80 63 Asynchronous Clock 0 OUT0 : Timer Output 0 to OUT3 : Timer Output 3 Pin name CLK0 : Timer Clock 0 to CLK3 : Timer Clock 3 Description Timer control signal pin These pins are used to input an external clock signal to the timer. In external clock mode these signals are synchronized with the internal clock. Input pin for count operation control signals to the timer In MODE0 through MODE3, the input signal is a gate signal. In MODE4, the pins input an external trigger signal. Timer output pin The output waveform is determined by the mode setting: * Periodic signal waveform output * Square wave output * One-shot pulse waveform output At reset, an "L" level signal is output. Prescaler asynchronous clock pin Input can be asynchronous with respect to the system clock signal input at the CLOCK pin. If an external clock signal is selected by the PRS0 and PRS1 registers, this signal can be used as a source clock for the prescaler. The clock signal divided by the prescaler is output at the PRSCK0, PRSCK1 pins. If these pins are not used, they should be fixed at "L" level.
IN0 : Timer Input 0 to IN3 : Timer Input 3
ACK1
I
69
Asynchronous Clock 1
PRSCK0 PRSCK1
O O
64 68
Prescaler Clock Output 0 Prescaler clock output pin Prescaler Clock Output 1 An "L" level signal is output at reset.
10
MB86941/942
4. SDTR SIGNALS (24)
Pin symbol DSR0# DSR1# RTS0# RTS1# DTR0# DTR1# CTS0# CTS1# I/O I I O O O O I I Pin no. 26 60 28 58 31 56 27 59 Pin name Data Set Ready 0 Data Set Ready 1 Request To Send 0 Request To Send 1 Data Terminal Ready 0 Data Terminal Ready 1 Clear To Send 0 Clear To Send 1 Description Modem control signal DSR input pin The status of these pins is indicated at the status register bit 7. Modem control signal RTS output pin Set the command register bit 5 to "1" to output an "L" signal, or to "0" to output an "H" signal. These pins can be used as a DATA TERMINAL READY signal or a RATE SELECT signal of modem.Set the command register bit 1 to "1" to output an "L" signal, or to "0" to output an "H" signal. Modem CLEAR TO SEND pin To enable sending, the command register bit 0 must be set to "1" and also an "L" level signal must be input at these pins. Transmit Data pin Parallel data written to the data register is converted to serial data and output from these pins. In asynchronous mode, a start bit and stop bit are attached, and a parity bit may be attached if necessary. If there is no data to be sent in the SDTR module, in synchronous mode a synchronizing character is output and in asynchronous mode the pins go to mark mode. If a send-prohibited setting (command register bit 0 set to "0") is in effect, or if an "H" signal is input at the CTS# pin, these pins to mark mode. However if a send-prohibited setting is entered while a sending operation is in progress, all sending data already written will be sent before these pins go to mark mode. In addition, in bisynchronous mode if the first synchronization character is being sent (synchronization standby), then these pins will go to mark mode after sending the second synchronization character. These pins indicate whether sending data is present. If there is no data to be sent in the SDTR module, the signal level is "H." As soon as one byte of sending data is written, these pins go to "L" level at the fall of the write signal. Transmit Ready output pin When the CTS# signal is "L" and the command register is set to enable sending, these pins send an "H" level signal whenever the sending data buffer is empty.
TRNDT0
O
29
Transmit Data 0
TRNDT1
O
57
Transmit Data 1
TEMP0 TEMP1 TRDY0 TRDY1
O O O O
42 46 33 52
Transmit Empty 0 Transmit Empty 1 Transmit Ready 0 Transmit Ready 1
(Continued)
11
MB86941/942
Pin symbol
I/O
Pin no.
Pin name
Description Transmit Clock input pin In synchronous mode, the sending bit rate is fixed at the sending clock x1, so that the clock signal input at these pins becomes the sending bit rate. In asynchronous mode, the sending bit rate will be the sending clock signal x1, or x1/16, or x1/64 depending on the bit rate setting in the mode register. For example, if a 19.2 kHz clock signal is input at the TCLK# pin, the sending bit rate will be 19200 pbs with an x1 setting, or 1200 pbs with an x1/16 setting, or 300 pbs with an x1/64 setting. Sending data is output in synchronization with the falling edge of the sending clock signal. Receive Data input pin Serial data input to these pins is converted to parallel data in the SDTR module and then can be read by the data bus. Receive Clock input pin In synchronous mode, the receiving bit rate is fixed at the receiving clock x1, so that the clock signal input at these pins becomes the receiving bit rate. In asynchronous mode, the receiving bit rate will be the sending clock signal x1, or x1/16, or x1/64 depending on the bit rate setting in the mode register. For example, if a 19.2 kHz clock signal is input at the RCLK pin, the receiving bit rate will be 19200 pbs with an x1 setting, or 1200 pbs with an x1/16 setting, or 300pbs with an x1/64 setting. Receiving data is sampled in synchronization with the rising edge of the receiving clock signal. Note that in asynchronous mode x1 speed differs from x1/16 and x1/64 speeds in that external synchronization of the RCLK and RCVDT signals is required.
TCLK0#
I
41
Transmit Clock 0
TCLK1#
I
48
Transmit Clock 1
RCVDT0 RCVDT1
I I
40 50
Receive Data 0 Receive Data 1
RCLK0
I
34
Receive Clock 0
RCLK1
I
51
Receive Clock 1
(Continued)
12
MB86941/942
(Continued)
Pin symbol I/O Pin no. Pin name Description These pins can function as synchronization detect input, synchronization detect output, or break detect output pins, depending on the mode setting. * External synchronization mode setting: Synchronization signals are input at these pins. When the RCLK is "H" level and these pins receive an "H" signal in hunting operation, the data sampled at the next rise of RCLK is the starting bit of the receiving data. * Internal synchronization mode: These pins are used as the synchronization character detect output pins. When incoming data matches the synchronization character register setting (both characters must match in bisynchronous mode), an "H" signal is output here. Next, the status register is read and this signal returns to "L" at the end of the read signal. * Asynchronous mode: These pins function as break detect output pins. Immediately after a framing error, an "H" signal is output if all receiving data values (one frame including start bit, parity bit, and stop bit) are "0." This "H" signal is cancelled if a "1" data is received before a reset is applied. Receive Ready output pin These pins are "H" level, when serial data received at the RCVDT0, RCVDT1 pins is converted to parallel data in the SDTR module and is in readable form. Then after the received data is read, these pins becomes "L" level at the end of the read signal.
SYBRK0
I/O
32
Synchronous/Break Detect 0
SYBRK1
I/O
53
Synchronous/Break Detect 1
RRDY0
O
43
Receive Ready 0
RRDY1
O
44
Receive Ready 1
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MB86941/942
5. RCSTG SIGNALS (11)
Pin symbol CS0# CS1# CS2# CS3# I/O O O O O Pin no. 16 21 24 25 Pin name Expansion Chip Select 0 Description
Expansion Chip Select output pin Expansion Chip Select 1 When the input to the RCS# pin is "L," one of these Expansion Chip Select 2 chip select signals will be active depending on the combination of input signals to the A0, A1 pins. Expansion Chip Select 3 Expansion Read Enable output pin When the input to the RCS# pin is "L" and a bus cycle Expansion Read Enable begins with an "H" input to the RD/WR# pin, this pin produces a pulse of the designated width and the designated timing. Expansion Write Enable output pin When the input to the RCS# pin is "L" and a bus cycle Expansion Write Enable begins with an "L" input to the RD/WR# pin, this pin produces a pulse of the designated width and the designated timing. Expansion Data Strobe Expansion Data Strobe output pin When a bus cycle begins with the RCS# pin input at "L" level, this pin produces a pulse of the designated width and the designated timing. Resource Chip Select pin. This pin is used to input the chip select signal supplied to the module RCSTG. When the module RCSTG is used to generate the external resource chip select signals CS0# to CS3#, read strobe RE#, write strobe WE#, and data strobe DS#, the corresponding areas must be decoded. This pin has internal pull-up resistance (MB86941 only). These are the input pins for the address signal to the module RCSTG. When the module RCSTG is used to generate the external resource chip select signals CS0# to CS3#, read strobe signal RE#, write strobe signal WE#, and data strobe signal DS#, this address input signal is used to designate the byte position in the corresponding area. When the input to the RCS# pins is "L"' level, the input signal to these pins determines which of the external resource chip select signals CS0# to CS3# goes active. These pins have internal pull-up resistance (MB86941 only). This is the output pin for the ready signal generated by the module RCSTG. When the module RCSTG is used to generate the external resource chip select signals CS0#-CS3#, read strobe signal RE#, write strobe signal WE#, and data strobe signal DS#, the ready signal is output from these pins to the MPU. When any of the signals CS0# to CS1# is at "L" level, this signal is asserted with the designated timing interval.
RE#
O
35
WE#
O
36
DS#
O
47
RCS#
I
37
Resource Chip Select
A0
I
38
Address 0
A1
I
39
Address 1
RDYOUT#
O
49
Ready Out
14
MB86941/942
6. I/O PORT SIGNALS (16)
Pin symbol IPD0 IPD1 IPD2 IPD3 IPD4 IPD5 IPD6 IPD7 IPD8 IPD9 IPD10 IPD11 IPD12 IPD13 IPD14 IPD15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin no. 72 78 84 85 86 87 94 95 96 98 99 103 104 105 106 107 Pin name I/O Port 0 I/O Port 1 I/O Port 2 I/O Port 3 I/O Port 4 I/O Port 5 I/O Port 6 I/O Port 7 I/O Port 8 I/O Port 9 I/O Port 10 I/O Port 11 I/O Port 12 I/O Port 13 I/O Port 14 I/O Port 15 Signal I/O port These pins may be used for input or output, as determined by register setting. These pins have internal pull-up resistance (MB86941 only). Description
7. SIO SIGNALS (4)
Pin symbol I/O Pin no. Pin name Description This is the input/output pin for the clock signal used for SIO serial data transfer. In external clock mode, the clock signal for serial data transfer is input at this pin. In internal clock mode, the clock signal from the internal clock generator is output at this pin. This pin has internal pull-up resistance (MB86941 only). SIO Receive Data input pin This pin receives data input LSB first, synchronously with the SICLK pin clock signal. This pin has internal pull-up resistance (MB86941 only). SIO Transmit Data output pin This pin outputs data LSB first, synchronously with the SICLK pin clock signal. SIO Interrupt Request output pin
SICLK
I/O
114
SIO Clock
SIRXD
I
109
SIO Receive Data
SITXD SIIRQ
O O
110 111
SIO Transmit Data SIO Interrupt Request
15
MB86941/942
8. VDD, VSS, N.C. (24/25)
Pin symbol VDD I/O Pin no. 1, 18, 54, 73, 90, 126 Pin name Description Power supply input pin
VSS
9, 19, 30, 45, 55, 66, 81, 91, 102, 117, 127, 138 97, 108, 112, 115, 116, 123 (17*)
Grand pin
N.C.
These pins shall be used as an open pin. No. 17 is also an open pin for MB86942.
* : No.17 is a READY2# pin for MB86941.
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MB86941/942
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output voltage Storage temperature Symbol VDD VI VO TSTG *3 Output current*2 IO At maximum VDD *4 *5 *1: *2: *3: *4: *5: VO = VDD VO = 0 VO = VDD VO = 0 VO = 0 Rating MB86941 -0.5 to +0.6*1 -0.5 to VDD + 0.5* -0.3 to VDD + 0.5*
1 1 1
MB86942 -0.5 to +4.0*1 -0.5 to VDD + 0.5* -40 to 125 +40 -40 +80 -40 VO = 0 -60 -80 VO = VDD +60
Unit V V V C
mA
VO = VDD +120
VSS = 0 V At 1 pin for 1 second Output pins other than D < 15 : 0 >, READY1# and REDY2# D < 15 : 0 > READY1#, READY2#
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Operating temperature Symbol VDD TA Value MB86941 4.75 to 5.25 0 to +70 MB86942 3.15 to 3.45 Unit V C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB86941/942
s ELECTRIC CHARACTERISTICS
1. DC Characteristics
(1) Input Characteristics (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter Symbol Condition CLOCK "H" level input voltage VIH IRQ15 to IRQ1 Other "L" level input voltage VIL IRQ15 to IRQ1 Other MB86941 Min. 2.8 2.4 2.2 VSS VSS Max. VDD VDD VDD 0.6 0.8 VSS VDD x 0.25 V VDD x 0.65 VDD + 0.15 V MB86942 Min. Max. Unit
(2) Output Characteristics (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter Symbol Condition IOH = -8 mA*2 "H" level output voltage VOH IOH = -3.2 mA*3 IOH = -4 mA*4 IOL = +12 mA*1 "L" level output voltage VOL IOL = +8 mA*2 IOL = +3.2 mA* IOL = +4 mA*4 *1: *2: *3: *4:
3
MB86941 Min. 4.0 -- VSS -- Max. VDD -- 0.4 --
MB86942 Min. -- VDD - 0.5 -- VSS Max. -- VDD -- 0.4
Unit
V
V
MB86941 READY1#, READY2# MB86941 D < 15 : 0 > MB86941 Other than READY1#, READY2# and D < 15 : 0 > MB86942
(3) Power Supply Current (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter Power supply current Symbol ICC Condition -- MB86941 Min. -- Max. 230 -- MB86942 Min. Max. 190 Unit mA
18
MB86941/942
2. Capacitances
(VDD = VI = 0 V, f = 1 MHz, TA = +25C) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CI/O Value Min. -- -- -- Max. 16 16 16 Unit pF pF pF
3. AC Test Conditions
(1) Input/Output Signal Waveform
tR 90% 10% MB86941: 1.5 V MB86942: 1 / 2 x (VIH + VIL) tPHL MB86941 : 1.5 V MB86942: VDD / 2
tF VIH MB86941: 1.5 V MB86942: 1 / 2 x (VIH + VIL) tPLH MB86941: 1.5 V MB86942: VDD / 2 VOL tPZL MB86941: 1.5 V MB86942: VDD / 2 tPZH MB86941: 1.5 V MB86942: VDD / 2 tPLZ 0.5 V tPHZ 0.5 V
Input signal waveform Output delay
VIL VOH
Output enable/ disable
VOL VOH
tR, tF < 5 ns MB86941: VIH = CLOCK 2.8V, IRQ15 to IRQ1 2.4 V, Other 2.2 V, VIL = 0.4 V MB86942: VIH = VDD x 0.65, VIL = VDD x 0.25
19
MB86941/942
(2) Load Circuit
VDD R1 = 2 K SW1 MB86941/2 Output R2 = 2 K C VSS SW2 LSI tester
Condition Normal output Tri-state output (READY1#, READY2#) Bi-directional pin (D bus)
Load capacitance MB86941 60 pF 65 pF 85 pF MB86942 30 pF -- 30 pF
Signal transmit LH, HL LZ, ZL LZ, ZL
SW1 OFF ON OFF
SW2 OFF OFF ON
4. AC Characteristics
(1) Reset signal (Hardware reset) (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter Reset pulse width tCLK: See "(2) Clock Signals." Symbol tRSTW Value Min. 20 Max. -- Unit tCLK
tRSTW RESET#
20
MB86941/942
(2) Clock signal (CLOCK) (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter Clock cycle time Clock "H" pulse width Clock "L" pulse width Clock rise time Clock fall time Symbol tCLK tCLKH tCLKL tCLKR tCLKF MB86941 Min. 25 9 9 -- -- Max. -- -- -- 4 4 20 8 8 -- -- MB86942 Min. Max. -- -- -- 2 2 Unit ns ns ns ns ns
tCLKF tCLKH CLOCK tCLKL
tCLKR
tCLK
(3) MPU interface (Register read/write) (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) MB86941 Parameter AS# setup time AS# hold time CS# setup time CS# hold time RD/WR# setup time RD/WR# hold time RS < 5 : 0 > setup time RS < 5 : 0 > hold time READY1#, READY2# output delay time READY1#, READY2# hold time D < 15 : 0 > Output delay time at reading D < 15 : 0 > Output hold time at reading D < 15 : 0 > Input setup time at writing D < 15 : 0 > Input hold time at writing * : READY2# is available for MB86941. 21 Symbol WSEL = "H" Min. tASS tASH tCSS tCSH tRWS tRWH tRSS tRSH tRDYF tRDYH tODD tODH tIDS tIDH 11 0 8 0 13 0 8 0 0 5 0 5 11 0 Max. -- -- -- -- -- -- -- -- 18 20 21 25 -- -- WSEL = "L" Min. 7 0 5 0 9 0 5 0 0 5 0 5 7 0 Max. -- -- -- -- -- -- -- -- 18 20 23 25 -- -- MB86942 Min. 7 2 7 2 7 2 7 2 0 5 0 5 7 0 Max. -- -- -- -- -- -- -- -- 18 20 23 20 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
MB86941/942
* WSEL = "H"
CLOCK tASH tASS AS# tASH
tCSH CS#
tCSS
tCSH
tRWH RD/WR# tRSH RS < 5 : 0 >
tRWS
tRWH
tRSS
tRSH
High-Z READY1# READY2#*
tRDYF
tRDYH
High-Z MB86942: "H" level output
MB86942: "H" level output tODD tODH
D < 15 : 0 > at read
High-Z
High-Z
tIDS D < 15 : 0 > at write
tIDH
* : Only for MB86941.
22
MB86941/942
* WSEL = "L"
CLOCK tASH tASS AS# tASH
tCSH CS#
tCSS
tCSH
tRWH RD/WR#
tRWS
tRWH
tRSH RS < 5 : 0 >
tRSS
tRSH
High-Z READY1# READY2#* MB86942: "H" level output tODD D < 15 : 0 > at read
tRDYF
tRDYH
High-Z MB86942: "H" level output
tODH
High-Z
tIDS D < 15 : 0 > at write
tIDH
* : Only for MB86941.
23
MB86941/942
(4) Interrupt signal * Interrupt input pulse width (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter IRQ input "H" level pulse width*1 IRQ input "L" level pulse width* tCLK: See "(2) Clock Signals." *1: When the trigger mode is set for "H" level signal input or RISE-EDGE, a pulse of at least this width is received as a REQ-FF signal. Note that this rule does not guarantee that no interrupts less than this width will be received. *2: When the trigger mode is set for "L" level signal input or FALL-EDGE, a pulse of at least this width is received as a REQ-FF signal. Note that this rule does not guarantee that no interrupts less than this width will be received.
2
Symbol tIHW tILW
Value Min. 6 tCLK + 10 6 tCLK + 10 Max. -- --
Unit ns ns
tILW IRQx tIHW
24
MB86941/942
* Interrupt input clear (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Symbol tIRQS Value Min. 2 tCLK + 10 Max. -- Unit ns
Parameter IRQx clear setup time* tCLK: See "(2) Clock Signals."
* : This parameter means the condition of REQUEST CLEAR execution and is applied at level trigger modes.
IRQx (High Level Trigger)
IRQx (Low Level Trigger)
CLOCK
AS#
RD/WR#
tIRQS
REQ CLEAR
25
MB86941/942
* Interrupt level output (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Symbol tIRLCD tIRLMD Value Min. -- -- Max. 80 80 Unit ns ns
Parameter IRL < 3 : 0 > clear delay time IRL < 3 : 0 > mask delay time
CLOCK
AS#
CS#
RD/WR#
IRL clear IRL mask
RS < 5 : 0 >
High-Z READY1# READY2#* MB86942: "H" level output
High-Z MB86942: "H" level output tIRLMD, tIRLCD
IRS < 3 : 0 >
* : Only for MB86941.
26
MB86941/942
(5) Prescaler timer * Prescaler input (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter Prescaler input clock cycle time* Prescaler input clock "H" level width* Prescaler input clock "L" level width* Prescaler input clock rise time* Prescaler input clock fall time* Symbol tACK tACHW tACLW tACR tACF MB86941 Min. 50 22 22 -- -- Max. -- -- -- 5 5 40 15 15 -- -- MB86942 Min. Max. -- -- -- 5 5 Unit ns ns ns ns ns
* : Applied in prescaler external clock mode. When the prescaler output is used as a timer signal, the timer input clock requirements must be met.
tACHW ACLK0, ACLK1 tACK
tACF
tACLW
tACR
* Prescaler output (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter Prescaler output "L" level width* *
1, 3
Symbol tPSCLW tPSCHW tPSCLW tPSCHW
Standard Value 1 N-1 N 2M - 1 N 2M - 1
Unit tPCK*4 tPCK*4 tPCK*4 tPCK*4
Prescaler output "H" level width*1, *3 Prescaler output "L" level width*2, *3 Prescaler output "H" level width*2, *3
*1: Applied when the prescaler register SELECT field is set to "0." N: Value set in the prescaler register PRESCALE VALUE field *2: Applied when the prescaler register SELECT field is set to any value other than "0." M: Value set in the prescaler register SELECT field. N: Value set in the prescaler register PRESCALE VALUE field. *3: When the prescaler register SELECT field is set to "0," the PRSCKx output is fixed at "L" level. *4: tPCK has the following prescaler input clock period. Internal clock mode: tPCK = 2 tCLK (For tCLK, see "(2) Clock Signals") External clock mode: tPCK = tACK (For tACK, see "(5) Prescaler Timer Unit/Prescaler Input")
tPSCLW tPSCHW
PRSCK0, PRSCK1
27
MB86941/942
* Timer (at external clock mode) (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Symbol tTCKH tTCKL tGS tGH Value Min. 3 3 10 0 Max. -- -- -- -- Unit tCLK tCLK ns ns
Parameter Timer input clock "H" level width Timer input clock "L" level width GATE signal (IN pin) setup time (for CLKx) GATE signal (IN pin) hold time (for CLKx) tCLK: See "(2) Clock Signals".
tTCKH
tTCKL
tGS
tGH
CLKx
INx (as IN pin of EVENT set "L")
INx (as IN pin of EVENT set "H")
* Timer output 1 (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter OUT output delay time (for CLOCK) Symbol tOUTD1 Value Min. -- Max. 30 Unit ns
CLOCK tOUTD1 OUTx
28
MB86941/942
* Timer output 2 (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter OUT output delay time* tCLK: See "(2) Clock Signals". * : Applied to the following cases. * Setting mode (write to TCR). * After setting to MODE0, write to RELOAD register/read COUNT register. * After setting to MODE1, write to RELOAD register/read COUNT register. * After setting to MODE3, write to RELOAD register. Symbol tOUTD2 Value Min. -- Max. 3 tCLK + 30 Unit ns
CLOCK
AS#
CS#
RD/WR#
Set to MODE, read count
RS < 5 : 0 >
High-Z READY1# READY2#* MB86942: "H" level output High-Z MB86942: "H" level output
OUTx
tOUTD2
* : Only for MB86941.
29
MB86941/942
(6) SDTR * DSR#, RRDY (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter DSR# setup time for resistor read Interval from register read to RRDY off tCLK: See "(2) Clock Signals". Symbol tDSRS tRRDYL Value Min. 28 0 Max. -- 100 Unit tCLK ns
CLOCK
AS#
CS# RS < 5 : 0 >
RD/WR#
Register read
D < 15 : 0 >
High-Z READY1# READY2#* MB86942: "H" level output tDSRS DSR#
High-Z MB86942: "H" level output
RRDY tRRDYL
* : Only for MB86941.
30
MB86941/942
* DTR#, RTS#, TRDY (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Symbol tDTROD tRTSOD tTRDYOD Value Min. 0 0 0 Max. 40 40 100 Unit tCLK tCLK ns
Parameter Delay time from register write to DTR# output Delay time from register write to RTS# output Delay time from register write to TRDY output tCLK: See "(2) Clock Signals".
CLOCK
AS#
CS# RS < 5 : 0 >
RD/WR# Register write
D < 15 : 0 >
READY1# READY2#*
High-Z MB86942: "H" level output
High-Z MB86942: "H" level output
DSR#, RTS#
TRDY
tTRDYOD tRRDYL, tDTROD
* : Only for MB86941.
31
MB86941/942
* Command write cycle (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Symbol tCMDC tCMDC tCMDC Value Min. 14 20 40 Max. -- -- -- Unit tCLK tCLK tCLK
Parameter Command write cycle time (for initial value setup) Command write cycle time (for asynchronous mode) Command write cycle time (for synchronous mode) tCLK: See "(2) Clock Signals".
CLOCK

tCMDC
AS#
CS#
RD/WR#
READY1# READY2#*
* : Only for MB86941.
32
MB86941/942
* Transmit Clock and Transmit Data (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Syncroh mode, x 1 mode Min. 32 14 0 Max. -- -- 100 x1/16, x1/64 mode Min. 4 4 0 Max. -- -- 100 Unit tCLK tCLK ns
Parameter Transmit Clock "H" width Transmit Clock "L" width Interval from transmit clock falling to transmit data output tCLK: See "(2) Clock Signals".
Symbol tTCKHW tTCKLW tTCKDT
tTCKLW 64 TCLK# (x 1/64 mode) 1 2 3 30
tTCKHW 31 32 33 34 35 62 63 64 1 2
4 5
12 13
16 TCLK# (x 1/64 mode)
1
2
3
6
7
8
9
10
11
14
15
16
1
2
tTCKLW TCLK# (x 1 mode, Sync mode) tTCKDT TRNDT
tTCKHW
tTCKDT
33
MB86941/942
* Receive Clock and Receive Data (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Symbol tRCK tRCKHW tRCKLW tRDS tRDH Syncroh mode, x 1 mode Min. 62 12 7 6 6 Max. -- -- -- -- -- x1/16, x1/64 mode Min. 8 4 4 6 6 Max. -- -- -- -- -- Unit tCLK tCLK tCLK tCLK tCLK
Parameter Receive clock period Receive clock "H" width Receive clock "L" width Receive data setup time Receive data hold time tCLK: See "(2) Clock Signals".
RCLK (x 1 mode, Sync mode)
tRCKLW
tRCKHW
tRCK
tRDS
tRDH
RCVDT
tTCKDT
16 RCLK (x 1/16 mode)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
64 RCLK (x 1/64 mode)
1
2
3
30
31
32
33
34
35
62
63
64
1
2
tRCKLW
tRCK
34
MB86941/942
* SYBRK Signal Timing for External Synchronous mode (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Symbol tBRKS tBRKH Value Min. 0 10 Max. -- -- Unit tCLK tCLK
Parameter SYBRK setup time (for RCLK) SYBRK hold time (for RCLK) tCLK: See "(2) Clock Signals".
RCLK
SYBRK
tBRKH tBRKS
* Transmit and Receive Control Signal Timing (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter Delay time from TCLK# rising (last bit) to TRDY rising Delay time from TCLK# rising (last bit) to TEMP rising Delay time from RCLK rising (last bit) to RRDY rising Detection time from RCLK rising (last bit) to internal SYNC (SYBRK pin) Detection time RCLK rising (last bit) to internal SYNC (status data buffer register) tCLK: See "(2) Clock Signals". Symbol tTCKRDY tTCKEMP tRCKRDY tSYCD1 tSYCD2 Value Min. -- -- -- -- -- Max. 36 24 35 62 70 Unit tCLK tCLK tCLK tCLK tCLK
35
36
< 2 >: Status data buffer selection
<2> <1> <2> <1>
* Receive Timing Example 1 (Asynchronous mode, 5 data bits, Parity enable, 2 stop bits)
< 1 >: Control data buffer selection
MB86941/942
RS < 5 : 0 >
<1>
RCVDT D0 D1 D2 D3 D4 P S1 S2 Data 2 Error Reset D0 D1 D2 D3 D4 P S1 S2
D0 D1 D2 D3 D4 P S1 S2
D0 D1 D2 D3 D4 P S1 S2
Data 1
Write Strobe (Internal Signal)
RCVEN set
Error Reset
Data 2
Read Strobe (Internal Signal) tRCKRDY
RRDY
OERR bit Data 1 Loss
FERR bit Framing Error
SYBRK Break Pattern Detection
* Transmit Timing Example 1 (Asynchronous mode, 6 data bits, Parity enable, 2 stop bits)
< 1 >: Transmit data buffer selection
<1> <1> <2>
< 2 >: Control data buffer selection
RS < 5 : 0 >
<1>
<1>
...... < 2 >
TRNDT D0 D1 D2 D3 D4 D5 S1 S2 Data 2 Data 3 D0 D1 D2 D3
D0 D1 D2 D3 D4 D5 S1 S2
......
D0 D1 D2 D3 D4 D5 S1 S2 Data 4
Data 1
Write Strobe (Internal Signal)
......
Data 2 tTCKRDY Break Set Data 3 Break Clear Data 4
Data 1
TRDY bit
......
TRDY tTCKEMP
......
TEMP
......
......
CTS#
MB86941/942
37
38
< 2 >: Control data buffer selection
<1> < 2 > ...... < 2 > <1> <1>
MB86941/942
* Transmit Timing Example 2 (Synchronous mode, Bisynchronous mode, 5 data bits, Parity enable)
< 1 >: Transmit data buffer selection
RS < 5 : 0 >
<1>
TRNDT Synchronous Character 1 Data 2 Synchronous Character 2
D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P
......
D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 Data 3 Data 4
Data 1
Write Strobe (Internal Signal)
......
Data 2 Break Set Break Clear Data 3 Data 4
Data 1
TRDY bit
......
TRDY
......
TEMP
......
......
CTS#
* Transmit Timing Example 2 (Synchronous mode, Bisynchronous mode, 5 data bits, Parity enable)
<1> : CONTROL DATA BUFFER SELECTION
<2> <3> <2> <1> <2>
< 2> : RECIEVE DATA BUFFER SELECTION
<3>
RS < 5 : 0 >
<1>
<3> : STATUS DATA BUFFER SELECTION
D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P D0 D1 D2 D3 D4 P
RCVDT
Synchronous Character 1 Synchronous Character 2
DATA 1
DATA 2
DATA 3
Synchronous Character 1 Synchronous Character 2
WRITE STROBE (Internal signal)
STATUS
EMH, RCVEN set
ERROR RESET
READ STROBE (Internal signal)
DATA 1
DATA 3
Synchronous Character 1
STATUS
RRDY
tSYCD1
SYBRK
tSYCD2
SYBRK bit
OERR bit
MB86941/942
DATA 2 loss
39
MB86941/942
(7) RCSTG * Control Signal Output Timing (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter RCS# setup time RCS# hold time A < 1 : 0 > setup time A < 1 : 0 > hold time Delay time from RCS#, A1, A0 fix to CS3# to CS0# fix Delay time from CLOCK to RE#, WE#, DS# fix Symbol tRCSS tRCSH tADS tADH tECSD tECNTD MB86941 Min. 5 5 5 5 -- -- Max. -- -- -- -- 15 15 7 2 7 2 -- -- MB86942 Min. Max. -- -- -- -- 18 18 Unit ns ns ns ns ns ns
40
MB86941/942
* Register Read Control Signal Output Timing
CLOCK
AS# tRCSS RCS# tADS A<1:0> CS3# to CS0# tECSD
tRCSH
tADH
tECSD
RD/WR# DS# RE# WE# RDYOUT# tECNTD RD/WR# DS# RE# WE# RDYOUT# tECNTD tECNTD tECNTD tECNTD "H" tECNTD tECNTD tECNTD *1 *1 *1 *1
*2 "H" *2
*2
*2
*1: Set register RTR0, RTR1. *2: Set register WTR0, WTR1.
41
MB86941/942
(8) SIO * Control Signal Output Timing (MB86941: VDD = 5 V 5%, TA = 0 to +70C) (MB86942: VDD = 3.3 V 0.15 V, TA = 0 to +70C) Parameter SICLK rise time SICLK fall time Setup time from SICLK rise/fall to valid SIRXD at receiving Delay time from SICLK rise/fall to SITXD output at transmitting Hold time from SICLK rise/fall to valid SITXD Symbol tSCLKR tSCLKF tSRD tDTD tHTD Value Min. -- -- 80 -- 80 Max. 3 3 -- 30 -- Unit ns ns ns ns ns
SICLK
tSCLKR
tSCLKF
SICLK tSRD SIRXD
SICLK tDTD SITXD tHTD
42
MB86941/942
s NOTES ON USE
When the prescaler is used in external clock mode, and the prescaler output signal is used as the timer operating clock, use the following settings. Set the timer operating clock to 'External clock' (TCR bits 10, 9 = "01"), and connect the prescaler output pin PRSCK externally to the timer external clock input pin CLK. When the prescaler and timer are set to the following modes, the timer output signal OUT will not change at the anticipated time: Prescaler: External clock mode (PRESCALER REGISTER bit15 = "1"). Timer: Prescaler internal output signal used as operating clock, without using the external input pin (TCR bit 10, 9 = "10").
43
MB86941/942
s REGISTER MAP
Block name RS5 to RS0 (HEX) 00H Register name TM0 (TRIGGER MODE 0) TM1 (TRIGGER MODE 1) RS (REQ SENSE) RC (REQ CLEAR) MASK (MASK) IRL (IRL Latch/Clear) Reserved SDR0 (SDTR Data 0) SCSR0 (SDTR CM/ST 0) Reserved bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CH15
CH14
CH13
CH12
CH11
CH10
CH9
CH8
01H
CH7
CH6
CH5
CH4
CH3
CH2
CH1
--
--
02H IRC 03H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
--
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
--
04H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
IM
05H Reserved 06H 07H 08H SDTR 0 09H 0AH 0BH
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- --
-- -- --
-- -- --
CL -- -- -- --
IRL LATCH -- -- -- -- -- --
TRANSMIT DATA/ RECEIVE DATA CONTROL DATA/STATUS DATA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
Reserved
SDTR 1
SDR1 0CH (SDTR Dsta 1) SCSR1 0DH (SDTR CM/ST 1) 0EH 0FH 10H Reserved PRS0 (PRESCALE 0)
TRANSMIT DATA/ RECEIVE DATA CONTROL DATA/ STATUS DATA -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- EX
-- -- --
TEST
-- -- -- --
-- -- -- --
-- -- -- --
-- -- --
-- -- --
-- -- --
Reserved
PRESCALER0
SELECT
PRESCALE VALUE
(Continued)
44
MB86941/942
Block name
RS5 to RS0 (HEX) 11H
Register name
bit 15 14 IN 13 -- 12
TEST
11 CE
10 CS
9
8
7
6 IV
5
4 MODE
3
2
1 EVENT
0
TCR0 (TIMER OT CONTROL 0) RVR0 (RELOAD VALUE 0) CVR0 (COUNT VALUE 0) PRS1 (PRESCALE 1) EX
OCONT
TIMER 0
12H
RELOAD VALUE
13H
COUNT VALUE
PRESCALER1
14H
TEST
--
--
--
SELECT
PRESCALE VALUE
15H
TCR1 (TIMER OT CONTROL 1) RVR1 (RELOAD VALUE 1) CVR1 (COUNT VALUE 1) Reserved --
IN
--
TEST
CE
CS
OCONT
IV
MODE
EVENT
TIMER 1
16H
RELOAD VALUE
17H Reserved 18H 19H
COUNT VALUE -- IN -- -- --
TEST
-- CE
--
--
--
--
-- IV
--
-- MODE
--
--
-- EVENT
--
TCR2 (TIMER OT CONTROL 2) RVR2 (RELOAD VALUE 2) CVR2 (COUNT VALUE 2) --
CS
OCONT
TIMER 2
1AH
RELOAD VALUE
1BH Reserved
COUNT VALUE -- IN -- -- --
TEST
1CH Reserved
-- CE
--
--
--
--
-- IV
--
-- MODE
--
--
-- EVENT
--
TCR3 1DH (TIMER TO CONTROL 3) TIMER 3 1EH RVR3 (RELOAD VALUE 3) CVR3 (COUNT VALUE 3)
CS
OCONT
RELOAD VALUE
1FH
COUNT VALUE
(Continued)
45
MB86941/942
(Continued)
Block name RS5 to RS0 (HEX) 20H I/O PORT 21H Reserved 22H 23H 24H Register name PDR (PORT DATA) DCR (PORT DIRECTION) Reserved SCR (SERIAL CONTROL) STR (SERIAL STATUS) RDR (RECEIVE DATA) TDR (TRANSMIT DATA) TRR (TRANSFER RATE) Reserved RTR0 (READ TIMING 0) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PORT DATA
PORT DIRECTION -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
CONTROL
25H
--
--
--
--
--
--
--
--
--
--
--
--
STATUS
SIO
26H
--
--
--
--
--
--
--
--
RECEIVE DATA
27H
--
--
--
--
--
--
--
--
TRANSMIT DATA RATE SELECT -- -- -- -- -- -- -- -- --
28H 29H Reserved 2AH 2BH 2CH TIMING0
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- --
-- -- -- --
-- -- -- -- TREW TWEW TREW TWEW
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
-- -- -- --
TRDSW TWDSW TRDSW TWDSW
TREL TWEL TREL TWEL
TRDSL TWDSL TRDSL TWDSL
WTR0 2DH (WRITE TIMING 0) 2EH RTR1 (READ TIMING 1) WTR1 (WRITE TIMING 1)
TIMING1 2FH
46
MB86941/942
s ORDERING INFORMATION
Part number MB86941PFV MB86942PFV Package 144-pin Plastic QFP (FPT-144P-M03) 144-pin Plastic QFP (FPT-144P-M03) Remarks
47
MB86941/942
s PACKAGE DIMENSION
144-pin Plastic QFP (FPT-144P-M03)
22.600.20(.890.008)SQ 20.000.10(.787.004)SQ 3.85(.152)MAX
(Mounting height)
108 109 73 72
0.05(.002)MIN (STAND OFF)
17.50 (.689) REF INDEX
144 37
21.60 (.850) NOM
Details of "A" part 0.15(.006)
0.15(.006) 0.15(.006)MAX 0.40(.016)MAX
"A" Details of "B" part LEAD No.
1 36
0.50(.0197)TYP
0.200.10 (.008.004)
0.08(.003)
M
0.1250.05 (.005.002) 0 10
0.500.20(.020.008)
0.10(.004)
"B"
C
1995 FUJITSU LIMITED F144003S-2C-3
Dimensions in mm (inches)
48
MB86941/942
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9812 (c) FUJITSU LIMITED Printed in Japan
49

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